Bclr 68k

I was in the right place at the right time. In the late s I was a postgraduate working on digital data transmission and considering the use of microprocessors, rather than dedicated logic, at the time microprocessors were becoming available. For various reasons, I became involved with the Motorola family. The family, or 68K, was one of the first so- called bit microprocessors and a contemporary of Intel's Although the 68K was a new design, its architecture was influenced by minicomputers such as the PDP- The bit 68K had a bit architecture, ISA.

It is hard to believe that the 68K was sold as a bit machine, competing against other bit machines when it was a true bit machine. It was a bit machine only in the sense that the data bus was 16 bits wide. Registers and many interal operations addition, logical, shifting were all bit. The 68K initially enjoyed considerable success. Sega adopted the 68K for its Mega Drive Console. Like other companies, Motorola produced new versions of the 68K family with ISA enhancements and greater speed.

However, the 68K did not thrive. Even Apple eventually adopted the IA32 architecture. The 68K lives on today as a microcontroller family marketed by Freescale Semiconductor. The 68K became very popular in the world of computer architecture education and, for many, it was the preferred means of introducing the ISA to students.

The reason for this is simple. Moreover, Motorola created a large amount of teaching material for the 68K and several simulators were freely available in the public domain, which made the 68K an ideal vehicle for class use.

I have included this section on the 68K because it is interesting; it played a significant role in the history of computing; it is easy to understand, and because it probably represents the high- point of CISC ISA development. An important reason for including this section is that an excellent 68K assembly and simulator for teaching use is available.

You can download the editor and simulator as a Windows- based package from its website or from here using the version I downloaded on 5 March EASy68K is easy to use. You first edit a 68K program and then run it in simulation mode. Like the ARM and MIPS simulators, you can step through a program instruction by instruction and observe the way in which registers and memory change as a program is executed.

The 68K has 16 bit general- purpose registers. D0 to D7 are eight data registers and A0 to A7 are eight address or pointer registers.

The address registers are used only as pointers.There was only one tutorial I found that really pointed me in the right direction, and it was a guide by SonicRetro member redhotsonicthough his tutorial has a few holes in places which makes it sort of impractical. Please note, I have been getting a lot of emails regarding the simulator BSVCand a lot of the questions related to problems with using macros correctly. So chances areI cannot help you in that regard. Section 01 — Getting Started.

This section shows the basics of 68k assembly programming. Part Computer Memory. Memory Storage. Instruction Set Out. Homework Results Section 02 — Basic Instructions. In this section, we look at some basic instructions that are relatively simple to use.

Motorola 68000

The ADD Instruction. The SUB Instruction. The EXG Instruction. The CLR Instruction. Section 03 — Binary Instructions. This section deals with binary manipulation bit specific instructions. The NOT Instruction. The AND Instruction. The OR Instruction. Section 04 — Positive and Negative Instructions. This section looks at instructions that work with positive and negative.

We also look at other similar instructions too. Bit significance. Signed and Unsigned. The NEG Instruction. The EXT Instruction. Bit shifting. Section 05 — Program Flow Change. Here, we take a look at instructions that cause the 68k to jump to different locations to read different instructions. The PC Program Counter. The JMP Instruction.

The BRA Instruction.Although the ColdFire architecture is closely related to the x0, there are many simplifications to the instruction set. Nearly all of the differences are omissions from the x0 instruction set and addressing modes. This means that with a few important exceptions detailed belowa x0 instruction which is implemented in ColdFire behaves in exactly the same way under the two architectures.

In fact, almost all user-level and much supervisor-level ColdFire code can be run unchanged on a or later x0 processor apart from new instructions introduced in the Version 4 ColdFire core. The converse, however, is not the case.

In order to understand the ColdFire instruction set in relation to that of the x0, it helps to have an appreciation of why the simplifications have been made. The philosophy behind ColdFire is influenced by the success of RISC processors in providing high performance - for a given degree of chip complexity - by eliminating seldom-used instructions and complex addressing modes, and by regularizing the instruction set to make it easier for the hardware to optimize despatch of the instruction stream.

However, standard RISC processors such as the PowerPC achieve high performance at the expense of low code density, in part because all instructions are the same width generally 4 bytes and also because only very simple addressing modes are available. In addition, RISC processors do not allow direct modification of memory locations; all memory reads and writes have to go via registers.

This all means that programs compiled for RISC processors tend to be substantially larger than those compiled for CISC architectures such as the x0. This penalty does not greatly matter for desktop systems or servers with gigabytes of RAM, but for embedded applications it can be a significant disadvantage, both in terms of system cost and power consumption.

Some of the complex addressing modes - again not important for compilers - are eliminated, and the additional hardware complexities involved in supporting arithmetic operations on bytes and words also disappear.

In order to regularize the instruction stream, all ColdFire instructions are either 2, 4 or 6 bytes wide; this is why certain combinations of source and destination operands are not available. The ColdFire addressing modes are quite similar to those of the originali. Compared with a or later processor, the comparison is as follows:. Note that further restrictions may be imposed on the addressing modes supported by particular instructions, even if a particular addressing mode is itself available on ColdFire.

MULU and MULS producing a bit result are not implemented, but 16 x 16 producing bit, and 32 x 32 producing truncated bit, are available. W, EXTB.

Differences between ColdFire & 68K

L and EXT. L survive, as do MULx. W and MULx. Some arithmetic instructions cannot act directly on memory - the destination must be a register. This applies to:. Even where a particular memory addressing mode does exist in ColdFire, some instructions are subject to further restrictions. Often, this is because of the limit of six bytes as the maximum length of a single instruction.

Specific restrictions include:. It also means that user-mode code written for ColdFire can generally run unchanged on a x0 processor, provided the new ColdFire-only instructions are not used. However, there are a few subtle cases where the ColdFire instruction is not exactly the same as its x0 counterpart. This means that a x0 code sequence which checks for overflow on multiply may assemble and run under ColdFire, but give incorrect results. ASL and ASR also differ in that they do not set the overflow bit - but this is less likely to cause problems for real programs!

Various members of the family have different register sets available at the supervisor level. The most important simplification in ColdFire's supervisor-level model is that there is only one stack pointer, shared for all code including interrupts, supervisor-level services, and user code.

It follows from this that, on ColdFire, it is never safe to write below the stack, since any interrupt which occurs would overwrite the stored data. Writing below the stack, though not recommended, is possible in some x0 systems in user mode, because interrupts cause a switch to the Interrupt or Supervisor Stack Pointer. A further issue is that ColdFire processors automatically align the stack to a four-byte boundary when an exception occurs, which can cause problems if code is reading or writing at a fixed offset from the stack pointer.

In fact, it is strongly recommended for performance reasons that the ColdFire stack should be kept long-word aligned at all times. Version 4 of the ColdFire core architecture re-introduces some familiar x0 instructions, and also adds some new instructions. The main changes are:. Differences between x0 family and ColdFire Although the ColdFire architecture is closely related to the x0, there are many simplifications to the instruction set.The addition can either be done between two data registers or between two memory locations.

If performed on bytes in memory, only address register indirect with predecrement addressing can be used. This facilitates easy manipulation of multiple-precision BCD numbers. The extend bit is added along with the BCD bytes to allow this multiprecision data manipulation. Also note that the Zero flag is only changed if the result becomes non-zero.

Therefore, both the Extend and Zero bits in the condition code register should be preset before the operation is performed.

bclr 68k

The Extend bit would normally be preset to a zero to prevent extension on the first additionand the Zero bit to a one to preset a zero result prior to the first addition. Flags affected: The Extend, Zero, and Carry flags are affected as per the result of the operation. The state of the Negative and Ovreflow flags is undefined. It is possible to add bytes, words, or long words with this opcode. Either the source or destination or both must be a data register.

The source operand can be any memory location or data register, and the destination operand can also be any memory location or data register. Flags affected: The Extend, Negative, Zero, Overflow, and Carry flags are all affected as per the result of the addition.

As an address rather than data is being manipulated, the condition code flags are left unaltered. Only sign-extended words or long words can be added. The immediate operand can be any 8-,or bit value as specified by the. W, or. L opcode suffix. The destination can not be an address register or a program counter relative address. The destination can be a memory location, a data register, or an address register.

If it is an address register, the condition code flags are unaffected and the operand length can not be a byte. This operation takes the place of the increment instruction found on other processors. Flags affected: The Extend, Negative, Zero, Overflow, and Carry flags are all set as per the result of the addition unless the destination is an address register.

This allows multiple-precision additions to be performed. For this reason, the Zero flag is only affected when a non-zero result is obtained. This means that if multiple numbers are added together using ADDX, the Zero flag will stay reset if any of those numbers were non-zero. The number of bits can be 8, 16, or 32 as per the. One or both operands must be a data register. The destination can be a data register, memory, or one of two special cases: the condition code register, only a byte-length immediate value is allowed.

If the destination is the status register, only a word-length immediate value is allowed, and the processor must be in supervisor mode or a priviledge voilation will occur. W imm bit value, SR Privileged. Flags affected: The Overflow and Carry bits are reset, the Negative and Zero bits set as per the result, and the Extend bit is unaffected. If you are shifting a data register, the number of bits to be shifted can be specified as an immediate value or as a value in another data register.

The immediate value can be 1 to 8, whereas the data register can be 1 to 64 where zero acts as the 64 count.Unity itself and the idea of Unity are already two. So far in Section 03we have had instructions that alter binary data in sizes of bytes, words or long-words. However, what if you wanted to change one single specific bit, instead of several at once? These next three instructions are designed for that very purpose, please be aware that they have very much the same set-out and rules, hence the reason they are compiled together under a single part.

This instruction will set the bit number in the destination operand decided by the source operandsetting the bit to 1. Binary contents inside d0 with position number above. Above each one is a number to represent the bit. In the example above, the source operand is 0Eso, bit number 0E of d0 is set to Now d0 contains In binary: It is more or less that simple. This will set the 01 st bit of d Of course, the source operand can contain a number that is higher than 1F, so what happens when this instruction below is processed?

Since the highest bit setting is the 1Fth bit, anything higher wraps back around to 00 again. And so, the 07th bit is set. Anything higher, always wraps around The instruction only reads the first 5 bits of the source operand. An important thing to note, is that if the destination operand is a data register just like abovethen the size is always. You cannot have byte or word size for data registers. Now we shall look at performing the instruction on memory:.

Binary with position number above. The source operand is 04so the 04th bit is set:. This results in 50, which is then saved into memory:. If the destination operand is a memory location directly or via an address registerthe size is always. You cannot have word or long-word size for memory.

The source operand can be either an immediate value:. Or a data register:. It cannot be a memory location directly or via an address registeror an address register directly these below are invalid :.

The destination operand on the other hand can be a data register or a memory location directly or via an address register :. It cannot be an address register directly:. This instruction will clear the bit number in the destination operand decided by the source operandsetting the bit to 0.

Motorola 68000

This is pretty much the same as BSET, except having one difference:. It clears the bit, making it 0, instead of setting it as 1. The exact same rules apply. This instruction will change the bit number in the destination operand decided by the source operandsetting the bit from 0 to 1, or from 1 to 0. Again, same rules, one difference.

Say d0 contains EC:. If we use this instruction:.Although personal computers are approaching the power of mainframes, the way to get the most out of any processor is to know when to use assembly language.

The popular Motorola MC processor is a good example; it has a fairly regular instruction set and instructions to support features of such languages as Pascal and C.

Yet the instruction set is not perfectly orthogonal -- warts in the design and implementation make the architecture interesting for hand-coded assembly programs. The continuing usefulness of assembly language, even on this processor, is apparent in recent industry products.

The Macintosh ROM, for instance, is written entirely in assembly language, yielding considerable savings in memory and speed. In this article I'll survey some of the subtleties of the to help you avoid its pitfalls and exploit its oddities for better speed or memory use.

I assume that you have some experience using the ; if not, see the bibliography at the end of this article. Most of the 's "traps" have a reason behind them; unintuitive aspects of the processor may actually be more useful, easier to implement, or correct in the view of the designers. One trap is memory alignment.

Although the supports byte, word, and long-word operations, word and long-word operands must be aligned on word boundaries even addresses. This is because memory is grouped in words 2 bytes and accessed via a bit bus. Instructions must be word-aligned also, but assemblers and linkers normally do this for you. Another trap is stack direction. The stack "grows" toward low memory. To deallocate space or to discard previously pushed valuesadd to the stack pointer.

Equally confusing, when allocating local storage with the LINK instruction, you must specify a negative displacement to be added to the stack pointer. The stack pointer SP must stay word-aligned. If you push or pop a byte through the SPthe processor will move a word to or from the stack, placing the relevant byte in the high-order half of that word. Only the SP behaves this way; other address registers act the way you'd expect.

This may seem an anomaly in an orthogonal architecture, but the SP must stay word-aligned so that words and long words are pushed to even addresses.

Shift and rotate instructions can operate on the byte, word, or long-word part of a data register, but shifts of memory operands can be only word size. Data registers can be shifted by up to 32 bits if the shift count is specified in another register or by up to 8 bits if the shift count is a constant given in the instruction.

Memory can be shifted by only 1 bit. The syntax of two-operand instructions may be reversed from other machines you're used to.The design implements a bit instruction setwith bit registers and a bit internal data bus. The address bus is bits and does not use memory segmentationwhich made it popular with programmers.

bclr 68k

Internally, it uses a bit data ALU and two additional bit ALUs used mostly for addresses, [2] and has a bit external data bus. As one of the first widely available processors with a bit instruction set, and running at relatively high speeds for the era, the 68k was a popular design through the s. It was widely used in a new generation of personal computers with graphical user interfacesincluding the Apple MacintoshCommodore AmigaAtari ST and many others.

The 68k and pushed other designs, like the Zilog Z and National Semiconductorinto niche markets, and made Motorola a major player in the CPU space.

68k Microprocessor - Pseudo Instructions

The 68k was soon expanded with additional family members, implementing full bit ALUs as part of the growing Motorola series. The original 68k is generally software forward-compatible with the rest of the line despite being limited to a bit wide external bus. Motorola's first widely-produced CPU was the Motorola Although a capable design, it was eclipsed by more powerful designs, such as the Zilog Z80and less powerful but faster designs, such as the MOS As the sales prospects of the dimmed, Motorola began a totally new design to replace it.

The MACSS aimed to develop an entirely new architecture without backward compatibility with the It ultimately did retain a bus protocol compatibility mode for existing peripheral devices, and a version with an 8-bit data bus was produced. However, the designers mainly focused on the future, or forward compatibilitywhich gave the design a head start against later bit instruction set architectures.

In the mid s, the 8-bit microprocessor manufacturers raced to introduce the bit generation. Arriving late to the bit arena afforded the new processor more transistors roughly 40, [ citation needed ] active versus 20, active in thebit macroinstructions, and acclaimed general ease of use.

Formally introduced in September[4] initial samples were released in Februarywith production chips available over the counter in November.

Rhines wrote that thus "Motorola, with its superior technology, lost the single most important design contest of the last 50 years". The was used in the first generation of desktop laser printersincluding the original Apple Inc.

Inthe received a minor update to its ISA to support virtual memory and to conform to the Popek and Goldberg virtualization requirements.

The updated chip was called the To support lower-cost systems and control applications with smaller memory sizes, Motorola introduced the 8-bit compatible MCalso in This was a with an 8-bit data bus and a smaller bit address bus.

AfterMotorola devoted more attention to the and projects. Several other companies were second-source manufacturers of the HMOS These included Hitachi HDwho shrank the feature size to 2.